Dr. Aaron Franklin 

​Nanomaterials for a New Era of Electronic Devices: Extending and Transforming the Trend


Abstract
Silicon-based electronics remain the backbone of the ongoing digital revolution and continue to enhance computational ability, as well as the accessibility of data.  As the range of possible applications for electronics grows, so does the realization that there are distinct limits to what silicon can do.  Meanwhile, nanomaterials have been studied for decades for their attractive electronic properties coupled with mechanical flexibility, thermal resilience, and compatibility with solution-phase processing.  From 1D carbon nanotubes (CNTs) to 2D graphene and transition metal dichalcogenides (TMDs), there is a growing list of nanomaterial options.  Making use of the unique attributes offered by nanomaterials opens the way for new types of electronics that add value far beyond Moore’s law-related improvements, effectively transforming the traditional trend.  In this talk, three distinct electronic applications employing nanomaterials will be discussed: 1) scalable low-voltage transistors, 2) printed electronic systems, and 3) ultrasensitive biological sensing.  Each of these applications relies on capabilities that are unique to nanomaterials, which leads to performance, fabrication, and/or function that are not possible with traditional semiconductors.  For instance, the low-cost printing of electronic sensors that must be mechanically flexible and able to operate within harsh environments, where silicon cannot survive.  Additionally, low-voltage negative capacitance transistors with 2D TMD channels that can provide both voltage and size scalability in sub-10 nm technologies for future computing applications.  Finally, fully printed biomedical immunoassays will be shown that offer a path for revolutionizing point-of-care diagnostic healthcare based on the extreme sensitivity of carbon nanotubes.  As the coverage of this talk will be relatively broad in terms of applications, the primary takeaway will be an overview of a new era of electronics that is uniquely possible using nanomaterials.  For decades, Si-based electronics have established a trend for devices and applications; nanomaterials hold the promise of extended and/or transforming that trend in the years to come. 

Bio
Dr. Aaron Franklin received his Ph.D. in Electrical Engineering from Purdue University in 2008 and then spent six years on the research staff at the IBM T. J. Watson Research Center in Yorktown Heights, NY.  In 2014, he joined the faculty at Duke University where he leads the Laboratory of Electronics from Nanomaterials, which has three primary research thrusts: 1) nanomaterials in high-performance nanoelectronic devices, 2) nanomaterial inks for low-cost printed electronics, and 3) harnessing nanomaterial sensitivity in biomedical applications. He is most widely known for his work on low-dimensional nanoelectronics with specific emphasis on carbon nanotube (CNT) transistors, including device scaling, transport studies, and advanced integration approaches.  Sponsored research in the Franklin lab includes projects involving high-performance transistors, printed electronics, thin-film transistors, supercapacitors, and biomedical sensors. In addition to research and academic accomplishments, Dr. Franklin is experienced in technology translation, holding more than 50 patents and successfully founding a funded company based on technology from his lab – printed electronic sensors for vehicle tires. 

 

Dr. Samar K. Saha
Planar CMOS Devices for Ultra-Low Power Applications at Nanometer Nodes

Abstract
In this presentation, planar CMOS device structures for low-power applications at nanometer nodes are discussed. It is well-known that he continuous scaling of MOSFETs towards their ultimate dimension near 5-nm regime has become more challenging due to their fundamental constraints such as short-channel effects (SCEs) and process-variability. The SCEs degrade the performance of scaled devices with higher sub-threshold swing and leakage current that pose a sever challenge to control device performance by gate bias. On the other hand, the process variability severely impacts the delay and power variability in VLSI devices, circuits, and systems. The impact of the increasing amount of within-die process variability on the yield of VLSI circuits, such as SRAM, has imposed an enormous challenge to design advanced System-on-Chips using bulk-CMOS technology. In order to mitigate the risk of process variability, new statistical design methodologies have evolved. Though, these statistical modeling techniques allow designers best possible solution to optimize the impact of variability, however, process variability constraint limits the circuit performance and yield. Therefore, to mitigate the risk of process variability, variability-tolerant device architectures are required. In this talk, the architecture and modeling of a novel variability-tolerant buried-halo MOSFET device structure is presented for low-power CMOS technology at nanometer nodes.
Bio
Dr. Samar K. Saha has been the President of IEEE Electron Devices Society (EDS) during 2016-2017, and is currently, Junior Past President of EDS. He is an Adjunct faculty in the Electrical Engineering department at Santa Clara University and a technical advisor at Prospicient Devices. Since 1984, he has worked at various positions for National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, Silterra USA, and SuVolta. He has, also, worked as a faculty member in the Electrical Engineering departments at Southern Illinois University at Carbondale, Illinois; Auburn University, Alabama; the University of Nevada at Las Vegas, Nevada;  and the University of Colorado at Colorado Springs; Colorado. He has authored over 100 research papers; one book entitled, Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond, CRC Press, Florida (2015); one book chapter on Technology Computer-Aided Design (TCAD), entitled, Introduction to Technology Computer-Aided Design, in Technology Computer Aided Design: Simulation for VLSI MOSFET, C.K. Sarkar (ed.): CRC Press, Florida (2013), and holds 12 US patents. His research interests include exploratory device and process architectures, TCAD, compact modeling, devices for renewable energy, and TCAD and R&D management. 
Dr. Scott Wedge
Predicting the Impact of Device Noise on Circuits and Systems

Abstract
As semiconductors continue to deliver faster speeds at reduced operating voltages, random noise and jitter become ever more crucial aspects of circuit design. The ability to analyze and minimize the impact of device noise in critical analog/mixed-signal blocks is especially essential. In recent years, several new noise analysis approaches have been established beyond the traditional linear time-invariant (LTI) approaches of the past. These powerful noise analyses – based on nonlinear, time & frequency domain, transient & periodic methods – can achieve excellent accuracy in predicting noise performance, but they still have limited ranges of usefulness and applicability. This presentation shall attempt to navigate the landscape spanning from device noise generation and noise influences on critical circuit blocks, to important noise metrics and measurements and methods for their accurate prediction. Guidelines, tradeoffs, and best practices regarding the various noise analysis solutions available shall be explored with the goal of achieving the best possible predictions of the impact of random noise on various circuits and systems.
Bio
Scott Wedge is a Principal R&D Engineer at Synopsys. He began his career as a circuit designer with Hughes Aircraft Company where he developed advanced mobile and satellite communications systems. A desire to create better design flows and software solutions for high-frequency ICs led him to EEsof, Hewlett-Packard, and Tanner Research. Scott served as Principal Investigator on multiple DARPA initiatives that developed advanced simulation and electronic design automation technologies. He has contributed to many popular RF and IC design tools over the years including PUFF, Touchstone, ADS, and Tanner AMS and MEMS Tools. Since joining the R&D team at Synopsys, Scott has contributed to many new HSPICE capabilities for signal integrity, RF, jitter, and noise analyses. He has authored numerous technical papers on circuit theory and design, including contributions to three textbooks. He is a registered P.E., a former Hughes Fellow, and a Senior Member of the IEEE. He received his Ph.D. from Caltech.

IEEE- Workshop on Microelectronics and Electron Devices (WMED)

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Mr. Russ Meyer

​Keynote Address


Abstract
The rapid progression of technology has continued to transform our lives.  The last decade has seen a fantastic transformation in how we interface with data and how technology is driving stronger interconnectivity with that data. These revolutions have been fueled by tremendous advances in memory technologies.  Over the next decade this is only expected to accelerate with stronger interconnectivity of the Internet of Things, the rapid adoption of autonomous driving, and with incredible advances in machine learning and artificial intelligence.  Memory technologies are critical in enabling the next waves of technology changes that will transform and enrich our lives.  Today, we will review these trends and discuss how the memory industry is reacting to meet the challenges of these new trends and realize the great opportunities they bring.
Bio
Russ Meyer has 24 years of experience in the memory industry.  Over those years he has been integrally involved in the development of several new memory technologies including DRAM, NAND, and 3D XPoint.  He is currently the Vice President of Non-Volatile Memory Integration at Micron Technology where he is directing the team responsible for the advanced development of these technologies.
Dr. Daniel Friedman
Considerations and implementations for high data rate serial link design

Abstract
Wireline transceivers are responsible for sending and receiving data from one chip to and from another.  The key specifications for such designs might include data rate, power consumption, area, and connection distance. The distance and data rate specifications, in particular,  drive the choice of physical channel to be used for the connection, which in turn will drive requirements such as the equalization capabilities of the transceiver. For short chip-to-chip channels with limited frequency-dependent loss, simple transceivers with little or no integrated equalization are appropriate.  For longer channels crossing backplanes and involving multiple transitions through connectors, complex transceivers with adaptive transmit and receive equalization are the right choice.  As connection distances grow even longer , optical interconnect becomes an attractive option. In this talk, a framework for understanding serial link design will be presented, including a discussion of basic equalization strategies and key challenges.  Next, several design examples will be presented, covering approaches to key classes of interconnect, from short reach channels to backplane channels to enabling highly integrated optical approaches.  The talk will conclude with a discussion of emerging directions in this field.
Bio
Dr. Daniel Friedman is currently a Distinguished Research Staff Member and Senior Manager of the Communication Circuits and Systems department of the IBM Thomas J. Watson Research Center. He received his doctorate from Harvard University in 1992 and subsequently completed post-doctoral work at Harvard and consulting work at MIT Lincoln labs, broadly in the area of image sensor design. After joining IBM in 1994, he initially developed field-powered RFID tags before turning to high data rate wireline and wireless communication. His current research interests include high-speed I/O design, PLL design, mmWave circuits and systems, and circuit/system approaches to enabling new computing paradigms. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the 2009 JSSC Best Paper Award (given in 2011), and the 2017 ISSCC Lewis Winner Outstanding Paper Award; he holds more than 50 patents and has authored or co-authored more than 75 publications. He was a member of the BCTM technical program committee from 2003-2008 and of the ISSCC international technical program committee from ISSCC 2009 through ISSCC 2016; he served as the Wireline sub-committee chair from ISSCC 2012 through ISSCC 2016. He has served as the Short Course Chair from ISSCC 2017 to the present, and is a member of the SSCS Adcom since 2018.
Mr. Scott Light
EUV Lithography’s Path to Manufacturing: Challenges and Opportunities

Abstract
After almost 30 years of development, Extreme Ultraviolet (EUV) lithography is finally moving into production, with several chip manufacturers announcing plans to begin EUV production in late 2018 or 2019.  This tutorial session will give a brief background on EUV technology, explain key industry challenges, and discuss how EUV fits into memory manufacturing.  The 13.5 nm wavelength of EUV light can print complex patterns with features below 20 nm, which allows one EUV pattern to replace several 193nm immersion patterning steps.  The EUV light source is complex, and EUV introduction has been delayed by low light intensity and system reliability.  ASML is delivering systems which meet source power requirements, but system availability is still not meeting manufacturing requirements.  Stochastic, or random, effects drive local CD variation and may cause missing or bridged patterns at smaller dimensions.  Reticle defects are another industry concern; the multilayer mirror makes it difficult to create a defect-free reticle, and the lack of a mature pellicle process increases the risk of particles falling onto the reticle.  The industry has focused on EUV applications for logic chips, but DRAM also has several applications where EUV offers benefits over 193nm immersion lithography.  This talk will explain the concepts behind the jargon, and give some context for how EUV will affect the industry.
Bio
Scott Light received a BS degree in Chemical Engineering from Rice University (Houston, Tx) in 1997.  He joined Micron in 1997, and has worked in numerous roles in the R&D Photolithography team.  He spent 2 years at IMEC in Belgium as Micron’s assignee to the 157nm lithography program.  He is currently leading the TD Photo Imaging Science team, working on new photo materials, EUV implementation, and DRAM roadmaps.  Mr. Light has co-authored approximately 10 conference papers and has over 25 patents. 
​Dr. Ehsan Afshari
Novel Circuit Design Techniques Inspired by Physics

Abstract
There are plenty of intriguing physical phenomena around us: from wave propagation in ocean to the movement of roller-coasters. These everyday examples can be used as inspiration in analog and RF circuit design. In this talk, we will show three examples of novel circuits that can achieve a much better performance compared to the conventional circuit topologies. The examples are focused on high speed, broadband, and low noise circuits. 
Bio
Ehsan Afshari was born in 1979. He received the B.Sc. degree in Electronics Engineering from the Sharif University of Technology, Tehran, Iran and the M.S. and Ph.D. degree in Electrical Engineering from the California Institute of Technology, Pasadena, in 2003, and 2006, respectively. In August 2006, he joined the faculty in Electrical and Computer Engineering at Cornell University as an Assistant Professor, and was promoted to Associate Professor in 2012. In Fall 2016, he joined the Electrical Engineering and Computer Science department at The University of Michigan at Ann Arbor, as an Associate Professor. His research interests are mm-wave and terahertz electronics and low-noise integrated circuits for applications in communication systems, sensing, and biomedical devices.

Prof. Afshari serves as the Distinguished Lecturer of the IEEE Solid-State Circuits Society and a member of the Technical Program Committee of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC). He was the chair of the IEEE Ithaca section, the chair of Cornell Highly Integrated Physical Systems (CHIPS), a member of International Technical Committee of the IEEE Solid-State Circuit Conference (ISSCC), a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems Society, a member of the Technical Program Committee of the IEEE Custom Integrated Circuits Conference (CICC), and a member of Technical Program Committee of the IEEE International Conference on Ultra-Wideband (ICUWB). He was awarded National Science Foundation CAREER award in 2010, Cornell College of Engineering Michael Tien excellence in teaching award in 2010, Defense Advanced Research Projects Agency (DARPA) Young Faculty Award in 2008, and Iran's Best Engineering Student award by the President of Iran in 2001. He is also the recipient of the best paper award in the Custom Integrated Circuits Conference (CICC), September 2003, the first place at Stanford-Berkeley-Caltech Inventors Challenge, March 2005, the best undergraduate paper award in Iranian Conference on Electrical Engineering, 1999, the recipient of the Silver Medal in the Physics Olympiad in 1997, and the recipient of the Award of Excellence in Engineering Education from Association of Professors and Scholars of Iranian Heritage (APSIH), May 2004.
Dr. Robert M. Wallace
Physical Characterization of Advanced Device Materials

Abstract
A variety of materials are now under investigation for advanced device concepts and applications.  In addition to establishing materials properties in the context of device physics and potential performance, an understanding of the integration constraints and the impact on the materials interfaces must also be addressed, as interfaces with contacts and dielectrics dominate device characteristics. This tutorial will focus on the physical characterization aspects of such advanced device materials, such as high-mobility and 2D materials, complex oxides, and nitrides, as well as the role of impurities and defects in these materials.  Topics in advanced device materials development and metrology to be covered include:
  1. Detection limits of characterization techniques
  2. In-situ vs. ex-situ characterization
  3. Surface and interface analysis methods
  4. Electron and ion mass spectrometry methods
The physics of the characterization/metrology techniques will be discussed, and examples of correlating such physical and chemical materials characterization to device behavior will also be presented.
Bio
Robert (“Bob”) M. Wallace (IEEE Fellow) is a Professor of Materials Science and Engineering and holds the Erik Jonsson Distinguished Chair in the Erik Jonsson School of Engineering and Computer Science at the University of Texas at Dallas.  He received his Ph. D. in Physics at the University of Pittsburgh in 1988.  After postdoctoral studies in Surface Chemistry at Pitt, Wallace joined the Central Research Labs at Texas Instruments in Dallas, where he performed and led advanced device materials characterization and development, including pioneering work on hafnium and zirconium-based high-k gate dielectrics.   In 2003, he joined the faculty at the University of Texas at Dallas, was a founding member of the Materials Science and Engineering program and facilitated the transformation of the program into a department to the current level of 15 faculty and more than 75 graduate students and postdocs. Wallace also has appointments in the Departments of Electrical Engineering, Mechanical Engineering, and Physics.
Wallace’s research program focuses on nanoelectronic materials and interfaces, and he currently leads the materials benchmarking and characterization research in the US nCORE NEWLIMITS Center. He has authored or co-authored over 375 publications in peer reviewed journals and proceedings, more than 225 contributed and 75 invited talks at international meetings and symposia, as well as 45 US and 27 international patents/applications. He was named Fellow of the AVS in 2007 and an IEEE Fellow in 2009 for his contributions to the field of high-k dielectrics in integrated circuits.